Comments (2)
robherring
commented on July 3, 2024
It is not really for the spec to decide what's the default for an arch and we try to keep architecture specifics out of it.
imho the ISA bindings totally make sense to be part of this document, but they ought to be in some document for sure.
Did you mean they should NOT be part of this doc? I'm not sure what you mean by ISA bindings? I assume that's CPU ISA, not ISA bus.
When moving ePAPR to the "DT Spec" we tried to remove PowerPCisms in the process. No doubt there are still some left. Patches welcome. :)
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andreiw
commented on July 3, 2024
Yeah I meant CPU ISA. I think my point is that the info needs to be somewhere (and I don't think it is anywhere at the moment). I don't know where I would look to answer the question of whether an architecture is or isn't by default cache coherent. Do you? Maybe it needs to be added somewhere in the DT bindings...I don't see it there.
Curiously qemu sets dma-coherent even on architectures where DMA is always coherent, like i386. Weird.
from devicetree-specification.
Related Issues (20)
- Interrupt parent phandle typos in interrupt-map example HOT 3
- cpu node requirements don't match schema HOT 9
- Rewrite the specs in Kaitai Struct and generate the text docs from KS specs HOT 2
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- MIME type for DeviceTree dts files HOT 5
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- Provide more information about RAM from the bootloader HOT 6
- Enforce ARRAY_SIZE(property) == ARRAY_SIZE(property-names) HOT 2
- enhancement: addition of /delete-label/ HOT 3
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- Table 1: Revision History was not updated for Release v0.4 HOT 1
- WARNING: Invalid device tree, expect boot to fail | openbsd-current Firefly RK3399 ARM SoC HOT 3
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