Comments (3)
I have not tested JTAG support recently, so I can't offer much advice right now. If I were testing this again, I would try the following next steps:
- Increase the openocd debug levels to verbose (
-d4
). It's probably a torrent of overly specific log info, but it might show something interesting. - Compare the logs using openocd with a known good JTAG adapter (preferably one that gives openocd full control, like an FT232H as opposed to a high-level adapter like the ST-Link) at the same nominal clock rate.
- As above, but also take a logic analyzer trace and decode it. I believe Sigrok/Pulseview have JTAG/SWD decoders.
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I don't have that type of logic analyzer... Will ULink 2 make a good reference adapter, since it with the latest firmware also uses CMSIS-DAP?
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Sigrok supports a fairly broad range of USB-based logic analyzers, but I understand if you don't want to add a software configuration problem on top of your hardware debugging problem.
The ULink2 seems like it would be a good reference from what you've described.
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Related Issues (14)
- schematic pdf hoặc png HOT 2
- can't work on bluepill HOT 5
- Using 4 pin front header on Blue Pill HOT 2
- Unable to flash Blue Pill HOT 6
- Compile dap42 for bulk transfer? HOT 4
- probetable.csv needs an update for Version >= v11.4.x
- Upgrade CMSIS-DAP to support RP2040 HOT 1
- Add programming instructions to README HOT 1
- Unable to flash stlink v2 clone HOT 4
- Implement USB CDC control lines (RTS, DTR) HOT 2
- Can not support M7 kernel KV56 HOT 2
- Build error ... HOT 2
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