Produced VHDL cannot be used within Vivado block designs about clash-compiler HOT 3 OPEN

I know we turn a bunch of things into std_logic_vector if you give flag -fclash-hdlsyn Vivado to clash but I forgot the details. Do you already specify that flag when you observe the problem?

If that flag doesn't do the job, would a flag that turns all ports of the topEntity into std_logic{,_vector} fit the bill or perhaps on all entities with a Synthesize annotation?

[edit]
Perhaps add -fclash-no-render-enums as well (which appears to be missing from the documentation)
[/edit]

from clash-compiler.

Indeed I observe the issue with -fclash-hdlsyn Vivado. Sadly -fclash-no-render-enums also does not appear to help.

In all cases I see things like:
clk : in wombat_types.clk_System; and s_axi_awvalid : in wombat_types.index_2

from clash-compiler.

A workaround would be to translate to Verilog instead. Whether this is usable entirely depends on your situation of course.

from clash-compiler.