Comments (1)
Thanks for reporting this! In the next release the variants will have the same type.
from clash-compiler.
Related Issues (20)
- Clash sometimes duplicates clockWizard HOT 1
- Expose `Clash.Class.Counter` methods HOT 9
- None of my code ends up in the synthesized Verilog output HOT 3
- VIO causes failure in `Clash.Netlist.BlackBox` HOT 2
- `IntegralTB` test fails with the SystemVerilog+Modelsim combination HOT 1
- PrimitiveGuard warnings are duplicated HOT 1
- BlackBoxHaskell blackboxes don't warn about potential primitive problems
- Clock primitive is duplicated HOT 4
- ILA ignores custom BitPack instances HOT 6
- Warn about out-of-range constants HOT 1
- Optimization flags are incompatible with the byte-code interpreter
- Bug: HDL generation failure with GHC 9.0.2, multiple hidden, synthesis attribute HOT 3
- Can't put synthesis attribute on output tuple
- Name duplication in generated Verilog for ClockWizard testbench HOT 3
- clash-lib doctest errors with GHC 9.4 on Debian HOT 5
- caseCon introduces free variables because of evaluator changes
- HDL generation failure with clash 1.8.1 ghc 9.4.7 HOT 14
- Example of a primitive in tutorial is outdated HOT 1
- We should document `OPAQUE` for primitives
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