Related Issues (20)
- systemverilog plugin: Segfault caused by localparam type in package
- synth_quicklogic name conflict HOT 3
- clockgating-plugin: not compiled; name mismatch HOT 1
- Unhelpful error message if passing no parameter to `read_systemverilog` HOT 1
- xdc-plugin: Setting DRIVE property breaks output HOT 3
- sv_plugin: unhandled typespec in process_typespec_member: HOT 5
- ERROR: member top_flag_t of a packed union has 3 bits, expecting 24 HOT 8
- Handling of "'1" expression HOT 3
- indices are mixed up when assigning values in array of array of packed struct HOT 8
- pmgen.py is downloaded without checking the cryptographic hash
- install commands don't respect DESTDIR to install into a stage directory HOT 1
- incorrect arithmetic shift HOT 6
- design_introspection-plugin missing README.md file
- Array Parameter Not Accepted HOT 6
- latest yosys: ast process_format_str() changed, plugin won't compile. HOT 4
- Not supported blocking and non-blocking assignments to the same array
- Not supported SystemVerilog bit vector functions HOT 1
- Not supported while loop
- Not supported while loop inside "initial" block
- f4pga-plugins conflicts with Yosys (recent versions)
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