Comments (4)
jerryz123
commented on June 9, 2024
from rocket-chip.
lordspacehog
commented on June 9, 2024
yeah, i think this is a good idea. I think it'd also be great to identify other parts to split out as well. The AMBA stuff would be pretty useful on it's own as a diplomatic interface implementation for example.
from rocket-chip.
lordspacehog
commented on June 9, 2024
@jerryz123 @sequencer Im starting work on this now. I opened an issue on the chisel repo to get input from them before i start sending PRs to them to upstream things from our utils. it would be great to get y'alls input on that ticket as well.
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sequencer
commented on June 9, 2024
You can split it into a new build.sc build target for now, and I'll take a look at them one by one to propose a concrete plan for deprecating or upstreaming to chisel stdlib.
from rocket-chip.
Related Issues (20)
- Remove Scalar Crypto HOT 4
- Embrace new world Chisel. HOT 12
- SimJTAG connecting to OpenOCD HOT 1
- How to Remove PTW from Rocket Core. HOT 2
- LR/SC unexpectedly fails when there is a jump in program HOT 1
- It is needed to clarify dependent tools version HOT 5
- Error in AXI4 Xbar with unused fields HOT 1
- Executing c.fld on Rocket chip load the wrong value in the destination register HOT 1
- Divide by zero on the Rocket chip and writes `0x0` to `rd` instead of `0xffffffffffffffff`
- REMU `x` by zero on the Rocket chip writes `0x0` to `rd` instead of `x` HOT 1
- "Hello world" simulation target and instruction in README.md
- can I remove the itim and tlb from the icache ? HOT 1
- Compile error on Chisel 6+ due to firrtl.options.RegisteredLibrary HOT 1
- Debugging with GCD Link broken
- Error in ./build.sh setp of rocket-tools HOT 1
- Code style, scalafix, and scalafmt discussion. HOT 1
- Generation of verilog file for rocket chip HOT 12
- parameter not find in freechips.rocketchip.config HOT 1
- [Proposal] Refactor the remaining helpers out of the diplomacy module in rocket-chip. HOT 5
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