Related Issues (20)
- Compilation fails HOT 3
- compile fail with TEST=dhry HOT 1
- Swerv RISC V HOT 2
- SRAM instance export HOT 3
- Remove (or make optional) the JTAG IDCODE command HOT 6
- Export ECC violation signals to the top level as status outputs
- Add support for DMI export to system
- Synthesis issue due to perr_dat_ff signal
- Improve readability and usability of common_defines.vh generated file
- UCR in synthesis
- Caliptra JTAG TdoEn missing output HOT 2
- CDC Error HOT 1
- LHS lesser than RHS : el2_ifu_mem_ctl.sv : ic_debug_way
- Simulation hits max cycle count for dhry, cmark_iccm, cmark_dccm HOT 11
- Does this design work with VCS/Cadence/Mentor simulators after memories were moved from design to tb_top? HOT 2
- Error while build through "make irun" HOT 7
- FuseSoC core description file is missing
- Request to review Lint Issues in Veer RTL HOT 2
- Relation between Core reset(rst_l) and dbg_rst_l
- EL2_DMA_CTRL.sv AXI interface the burst length mode, awlen & arlen is not used, it is Error ?
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