Comments (6)
- I keep recommending CAL, which is a journal for early-stage work: https://www.computer.org/csdl/journal/ca
- I didn’t see anything perfect in the ASPLOS workshops: https://asplos-conference.org/co-located-events/
- Nothing really relevant in the PLDI workshops, but that’s not exactly a surprise: https://conf.researchr.org/home/pldi-2020
- I don’t believe the lists of workshops are out for ISCA yet (and they may not be for a little while?), but we can keep an eye out.
from calyx.
- Probably way to hardware focused but about the right deadline: https://www.computer.org/digital-library/magazines/mi/call-for-papers-special-issue-on-chip-design-2020
- Seems relevant, accepts 4 page WIP papers, but probably too soon of a deadline (Feb 28) https://conf.researchr.org/home/LCTES-2020#Call-for-Papers
from calyx.
Huh, yeah, LCTES's topics are a little broader than I was expecting. We don't have anything to say about embedded systems but it seems like there are at least a few relevant people on the PC. We should consider it if we think we can get something good done in a few weeks!
from calyx.
https://conf.researchr.org/track/pldi-2020/pldi-2020-Student-Research-Competition possible but not really a "standard" paper format and only allows a single author
from calyx.
w.r.t to Cal, they accept papers on a rolling dealine with these categories. I don't exactly know which topic Futil would fall under, but maybe "Computers" or "Software Engineering". Computers accept short 8 page papers (with references) and Software Engineering accepts papers of any length less than 12.
from calyx.
- Individuals do enter the SRC, but this doesn't preclude any other form of "publication" (in the sense it's not really a publication; more of an in-person competition that you have to get into the first round of by writing something).
- I think what you're seeing there is a list of all the journals that the IEEE Computer Society offers. The second one on the list is CAL. Here is the author instructions for CAL, which says it's four pages.
from calyx.
Related Issues (20)
- Separate Out FSM in IR when during TDCC and `compile-static` HOT 21
- `cell-share` Needs a Timing-Based Heuristic or Cost Model HOT 1
- [Cider 2] Connect to fud2 and the existing test suites
- `fud`: remove dependency on `calyx-py`
- Builder: Support for Combinational Components HOT 1
- Docs: CIDR configuration instructions HOT 4
- Compilation bug: overeager cell sharing HOT 9
- Floating-point constants
- Combinational memories in `gen_exp` and `gen_ntt_pipeline` HOT 1
- [fud2] Mode that is friendly to parallel builds, with a unique per-run workdir name HOT 5
- Tracker: binary heaps HOT 3
- Allowing for nested `ref` cell instantiation HOT 3
- [fud2] Switch to custom testbench generation HOT 6
- [Cider Dap] Tracker
- Produce separate AXI channels for every memory in a Calyx program HOT 1
- Discussion: Introduce `dyn_mem_d1` primitive? HOT 2
- Question about Section 3 of the paper HOT 2
- Unexpected behavior with reading from `seq_mem` reference and `invoke` HOT 3
- Incomplete subtyping check on cells
- Nested `if` conditions that share combinational groups HOT 1
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from calyx.