bolifeyo,github

5-stage_risc-v_processor

Worked on a team of 3 to complete a pipelined RISC-V processor from scratch in System Verilog, complete with dual L1 Caches, a L2 cache, prefetching, and a branch predictor.

addernet

Code for paper " AdderNet: Do We Really Need Multiplications in Deep Learning?"

alpha-zero-general

A clean implementation based on AlphaZero for any game in any framework + tutorial + Othello/Gobang/TicTacToe/Connect4

arm_amba_design

Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.

armv7m-emulator

An ARMv7-M emulator, written in Go

axi4-interface

AXI4 and AXI4-Lite interface definitions

buildyolo

젯슨나노에서 YOLO v3 (GPU + CUDNN + OpneCV 전용) 설치하기

cmake-examples

Useful CMake Examples

computer-architecture

Detailed and step by step implementation of RISC-V CPU from scratch using Verilog. This work is part of my academic course EE2003, Introduction to Computer Organisation in IIT Madras.

confmc.examples

CON-FMC Examples for Version 2019.05

confmc.x86_64.linux.2020.06

CON-FMC SW package version 2020.06 for 64-bit Linux

confmc.x86_64.mingw.2019.10

CON-FMC SW package version 2019.10 for 64-bit MinGW/Windows

cpu-on-vivado-hls

A simple MIPS-like CPU demo in C++ for Xilinx Vivado HLS

cs231n-project

CNN accelerator

darknet_ros

YOLO ROS: Real-Time Object Detection for ROS

data-structures-and-algorithms-python

All the essential resources and template code needed to understand and practice data structures and algorithms in python with few small projects to demonstrate their practical application.

databook_python

IPython notebooks with demo code intended as a companion to the book "Data-Driven Science and Engineering: Machine Learning, Dynamical Systems, and Control" by Steven L. Brunton and J. Nathan Kutz