Bart Pleiter's Projects
ASR punctuation restoration experiments for the ASR Master course at Radboud University
A project for the course Operating Systems :p
MIDI wavetable synthesizer for ESP32
A completely self designed (game) computer, implemented in hardware using an FPGA. Basically every component is self designed, from the ISA up to the PCB and software. Project exists to learn more about the fundamentals of computers and to improve my Verilog skills
Redesign and continuation of the FPGC5 but with a pipelined CPU (with hazard detection, branch prediction, etc.), memory cache (L1 and L2), and a better architecture for running BCC code
Tetris project for Natural Computing 2021
AI for GameBoy Tetris on original hardware using a SNES, Super GameBoy, FPGA and MCU
Code repository for Master thesis on backdoor attacks on transformer-based DNNs for tabular data