Comments (2)
build
is not part of this repository. It was a script and its primary purpose was for designs that used Bluespec's host-to-FPGA communication mechanisms (BlueNoC and SceMi via BlueNoC). That mechanism was built using BSC: Bluespec provided BSV files and pre-generated IP for the FPGA side and C/C++ files for the host side, and the build
script knew where to find those specific files and compile them and synthesize an FPGA bitfile. None of those files have been included in this repo and so the build
script hasn't been included either.
My understanding is that the 6.375 labs don't use Bluespec's communication mechanism but instead use the Connectal mechanism (which has its own FPGA-side and host-side files). This shouldn't require the build
script.
from bsc.
Yes, you are correct. The recent version of the course uses Connectal as the interface mechanism. However the previous offerings did use Bluespec's interface mechanism.
Thanks anyway.
from bsc.
Related Issues (20)
- Can't Find basicinout file in Bluespec HOT 1
- Question about case expressions HOT 6
- Better positions for kind-mismatch errors
- bluesim simulation result is different from verilog simulation, does bluesim have bug implementing UInt#(n) when n is big (eg., 72)? HOT 1
- Bluesim leaves junk in loaded registers if the full range of hex digits isn't specified HOT 3
- uppercase names not allowed in interface property `arg_names` HOT 4
- bsc ignores `always_ready` when checking for duplicate wires
- module verilog does not allow sharing ports among conflicting methods
- Improve the mechanism for testing Bluespec Inc bug 1490 HOT 3
- `-dparsed` output produces invalid register updates with BSV HOT 2
- `-dparsed` produces invalid BSV module function that takes another module as an argument HOT 2
- Missing `Ord Bool` instance HOT 7
- Static check of file descriptor argument to tasks like $fgetc HOT 3
- Testsuite reports an error getting BSC version HOT 2
- Internal Compiler Error when quoting a character value. HOT 4
- Bluesim's symbol-probing interface has wrong values for FIFO
- Unresolved numeric contexts that should be resolvable HOT 6
- Verilog import fails in macro substitution HOT 2
- Unexpected syntax error HOT 1
- expandPorts.tcl has hardcoded paths which do not exist. HOT 1
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from bsc.