Related Issues (20)
- Support a "clocked_by" syntax in BH module instantiations
- i got several error onthe installation process HOT 4
- Nondeterminism in ISyntax definition order
- bs classic: struct update syntax of struct from `import qualified` gives error for the wrong file. HOT 2
- Better distinguish between qualified imports and sub-imports
- assertion checks should have knowledge of rwire/creg internals HOT 5
- consider a name different from "core" inside the bin directory
- Support superclasses with (dependent) type variables not in the base typeclass HOT 3
- Any way to get the RDY signal for a method? HOT 7
- Method with internal input-dependent "if" mistakenly scheduled as SBR to self HOT 5
- `mkRegFileFullLoad` does not actually `Load` if `index_t` is 0 bits. HOT 8
- Can't Find basicinout file in Bluespec HOT 1
- Question about case expressions HOT 6
- Better positions for kind-mismatch errors
- bluesim simulation result is different from verilog simulation, does bluesim have bug implementing UInt#(n) when n is big (eg., 72)? HOT 1
- Bluesim leaves junk in loaded registers if the full range of hex digits isn't specified HOT 3
- uppercase names not allowed in interface property `arg_names` HOT 4
- bsc ignores `always_ready` when checking for duplicate wires
- module verilog does not allow sharing ports among conflicting methods
- Improve the mechanism for testing Bluespec Inc bug 1490 HOT 3
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