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  • 👋 Hi, I’m avishek
  • 👀 I’m interested in anything that incorporates both hardware as well as software
  • 💞️ I’m looking to collaborate on projects around the idea of ML and electronics
  • 📫 How to reach me- '[email protected]'



Tech Stack

Python  C++  Django  Flask  Bootstrap
HTML  CSS  Git  Visual Studio Code  Verilog  System Verilog 

Avishek's GitHub stats

Avishek Choudhary's Projects

open-pixel-art icon open-pixel-art

A collaborative pixel art project to teach people how to contribute to open-source

vsd-iat-sign-off-timing-analysis---basics-to-advanced icon vsd-iat-sign-off-timing-analysis---basics-to-advanced

Static timing analysis (STA) is a method of validating the timing performance of a design by checking all possible paths for timing violations. STA breaks a design down into timing paths, calculates the signal propagation delay along each path, and checks for violations of timing constraints inside the design and at the input/output interface. The

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