arunjeevaraj Goto Github PK

asic_labs_fa21

async_fifo

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

fpga_labs_sp22

git_week3

This is for week 3 of git course from coursera powered by google.

guess_the_number

A remake of the classical guess the number game in nexys 4 FPGA board, using the AXI UART and custom made 7seg axi block with microblaze.

hdmi

Send video/audio over HDMI on an FPGA

hls_vector_array

hybrid_computing_thesis

iic-osic-tools

IIC-OSIC-TOOLS is an all-in-one Docker image for SKY130/GF180/IHP130-based analog and digital chip design. AMD64 and ARM64 are natively supported.

iot_course_coursera

it-cert-automation-practice

Google IT Automation with Python Professional Certificate - Practice files

jupyter

Jupyter metapackage for installation, docs and chat

learn-fpga

Learning FPGA, yosys, nextpnr, and RISC-V

learning_cpp

used for personal learning and lookback, for learning modern c++ program principles.

mpu

A SIMD based Matrix processor

onfi_controller

ONFI COMPLIANT controller repo.

python_for_everybody

Code developed as part of the assignments and exercises from coursera course specialization on python for everybody.

riscv_simple

sky130-10-bit-sar-adc

A 10bit SAR ADC in Sky130

sky130_sar-adc1

Fully-differential asynchronous non-binary 12-bit SAR-ADC in SKY130, free to re-use under Apache-2.0 license

sky130stdcelldesign

This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedures on how to create a custom LEF file and plugging it into an openlane flow.

sl_preceptron

trivia_c_launchpad_with_freertos

These are some of the FREE RTOS learning projects done with the Texas instruments Trivia C launchpad board that hosts a tm4c123gh6pm MCU.

uhdm-integration-tests

vco

High Speed VCO in Skywater 130nm

zipcpu

A small, light weight, RISC CPU soft core