angelterrones Goto Github PK

algol

A RISC-V CPU (Outdated: using priviledge v1.7)

algol_design

Presentación acerca de los pasos realizados para el diseño de mi procesador ALGOL (RV32IM)

alpaca-lora

Finetuning InstructLLaMA on consumer hardware

altair

A RV32I RISC-V soft processor using nMigen

angelterrones.github.io

antares

A MIPS32 release 1 processor.

aoc2020

Advent of Code 2020

aoc2021

Advent of Code 2021

banner-myhdl

bash_tutorials

I found these using archive.org on some site. I didn't write them though.

basic-verilog-project

Basic example of a 4-bit ALU, cosimulated using myHDL. Provides a makefile for synthesis (using Xilinx ISE)

bellatrix

A RV32I RISC-V soft processor using nMigen

bot_detector

Codes from the paper "Bots in social and interaction networks: Detection and impact estimation"

cortex

Production infrastructure for machine learning at scale

cronometro-usbbot

cv

darknet_ros

YOLO ROS: Real-Time Object Detection for ROS

dcrn

Distributed Control of Robotic Networks

dotfiles

Dotfiles for Arch Linux

ga-render

Algoritmo genético para replicar una imagen.

ga-render-circle

ga-render-cuda

GA for replicating an image, using CUDA.

ga-render-gui

lm32

LatticeMico32 soft processor

m2gl025-creative-board-notes

Notes from tinkering with Microsemi's IGLOO2 RISC-V development board.

mirfak

A RISC-V RV32IM CPU

musb

A MIPS32 release 1 processor (Do not use)

presentacionga-ccie

Presentación para CCIE

riscv-arch-test

riscv-formal

RISC-V Formal Verification Framework