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2d-binary-content-addressable-memory-bcam

Modular SRAM-based 2D hierarchical-search Binary Content Addressable Memory (2D-BCAM)

binary-to-bcd-converter

Parametric Binary to BCD Converter Using Double Dabble / Shift and Add 3 Algorithm

block-ram-based-heterogeneous-multi-ported-memory-compiler

cell-based-layout-compaction

Cell-based VLSI layout compaction algorithm based on a modified Segments tree data structure; programmed in Perl script

cell-based_mixed-timing_fifo.synopsys_flow

This package includes a complete design framework based on Synopsys tools for mixed asp* asynchronous and clocked synchronous cell-based FIFOs

cell-based_mixed_fifo.flow

This package includes a complete design framework for mixed asp* asynchronous and clocked synchronous cell-based FIFOs

dynamic-frequency-phase-sweeping

Dynamic Run-time Frequency and Phase Sweeping for Altera's PLLs with Freq. and Phase Meters

hierarchical-product-quantization-for-approximate-nearest-neighbors-search

Hierarchical Product Quantization for Approximate Nearest Neighbors Search - Initial release

indirectly-indexed-2d-binary-content-addressable-memory-bcam

Modular SRAM-based indirectly-indexed 2D hierarchical-search Binary Content Addressable Memory (II-2D-BCAM)

indirectly-indexed-2d-ternary-content-addressable-memory-tcam

Modular SRAM-based indirectly-indexed 2D hierarchical-search Ternary Content Addressable Memory (II-2D-TCAM)

interleaved-synthesizable-synchronization-fifos

Interleaved Architectures for High-Throughput Synthesizable Synchronization FIFOs

linear-feedback-shift-register-lfsr-counter

Linear Feedback Shift Register (LFSR); A periodic counter with random count

lut-input-permutations-enumerator

LUT-Input-Permutations-Enumerator; A permutations enumerator circuit based on Lehmer's code; synthesis and verification frameworks are provided

multi-fanout-kernighan-lin-hypergraph-bi-partitioning

An enhanced version of the Kernighan-Lin based bi-partitioning algorithm for circuits with multi-fanout nets.

multi-sink-lee-moore-shortest-path-maze-router

This is an implemention of Lee-Moore's Shortest Path Maze Router with multi-sink nets support.

multiported-ram

Modular Multi-ported SRAM-based Memory

multiported-ram-compiler

A Multi-Ported Memory Compiler Utilizing True Dual-Ported BRAMs

polygonal-layout-layer-arithmetics

Algorithmic VLSI layout layer arithmetic operations based on a modified Segments tree data structure for finding the contour of union of rectangles; programmed in Perl script

simulated-annealing-cell-based-placer

This is an implemention of a simulated-annealing standard-cell placement tool; The tool assigns physical locations to each cell in a circuit.

switched-multiported-ram

Switched SRAM-based Multi-ported RAM

timing-driven-variation-aware-clock-mesh-synthesis

Timing-Driven Variation-Aware Clock Mesh Synthesis Environment; programmed in Perl and TCL scripts

verilog-quartus-mapping-vqm-netlist-parser

generates a Comma-Separated Values (CSV) file of all nodes in a given Verilog Quartus Mapping (VQM) netlist and their respective fanouts, ordered by fanout (highest first)