Problem with booting OPTEE on HiKey board about documentation HOT 6 CLOSED

You're welcome. Sounds like something wrong with UART3. You might want double check your connection, cable, etc.

from documentation.

The only thing that comes to mind is if you have an SD card plugged into the board, try removing it first before booting.

from documentation.

There is not any SD card.
It is strange, i didn't have this problem before.

from documentation.

What is the reason that there is no grub_uart2.cfg in patches_hikey/grub/
But hikey.mk (in comments) said that we can select UART2 for Normal/secure world console?

I changed hikey.mk and set NW_CONSOL_UART=3. Now it passes the "load fastboot1" but break again with:

NOTICE: Booting Trusted Firmware
NOTICE: BL1: v2.2(release):v2.2
NOTICE: BL1: Built : 14:24:02, Jun 9 2021
NOTICE: BL1-FWU: FWU Process Started

debug EMMC boot: print init OK
debug EMMC boot: send RST_N .
debug EMMC boot: start eMMC boot......
load fastboot1!
NOTICE: BL2: v2.2(release):v2.2
NOTICE: BL2: Built : 14:24:03, Jun 9 2021
NOTICE: acpu_dvfs_set_freq: set acpu freq success!NOTICE: BL2: Booting BL31
NOTICE: BL31: v2.2(release):v2.2
NOTICE: BL31: Built : 14:24:03, D/TC:0 plat_get_aslr_seed:109 Warning: no ASLR seed
D/TC:0 add_phys_mem:564 TEE_SHMEM_START type NSEC_SHM 0x3ee00000 size 0x00200000
D/TC:0 add_phys_mem:564 TA_RAM_START type TA_RAM 0x3f200000 size 0x00e00000
D/TC:0 add_phys_mem:564 VCORE_UNPG_RW_PA type TEE_RAM_RW 0x3f063000 size 0x0019d000
D/TC:0 add_phys_mem:564 VCORE_UNPG_RX_PA type TEE_RAM_RX 0x3f000000 size 0x00063000
D/TC:0 add_phys_mem:564 ROUNDDOWN(0xF7106000, CORE_MMU_PGDIR_SIZE) type IO_NSEC 0xf7000000 size 0x00200000
D/TC:0 add_phys_mem:564 ROUNDDOWN(0xF7022000, CORE_MMU_PGDIR_SIZE) type IO_NSEC 0xf7000000 size 0x00200000
D/TC:0 add_phys_mem:578 Physical mem map overlaps 0xf7000000
D/TC:0 add_phys_mem:564 ROUNDDOWN(0xF7010800, CORE_MMU_PGDIR_SIZE) type IO_NSEC 0xf7000000 size 0x00200000
D/TC:0 add_phys_mem:578 Physical mem map overlaps 0xf7000000
D/TC:0 add_phys_mem:564 ROUNDDOWN(0xF7010000, CORE_MMU_PGDIR_SIZE) type IO_NSEC 0xf7000000 size 0x00200000
D/TC:0 add_phys_mem:578 Physical mem map overlaps 0xf7000000
D/TC:0 add_phys_mem:564 ROUNDDOWN(0xF7030000, CORE_MMU_PGDIR_SIZE) type IO_NSEC 0xf7000000 size 0x00200000
D/TC:0 add_phys_mem:578 Physical mem map overlaps 0xf7000000
D/TC:0 add_phys_mem:564 ROUNDDOWN(0xF8000000, CORE_MMU_PGDIR_SIZE) type IO_NSEC 0xf8000000 size 0x00200000
D/TC:0 add_phys_mem:564 ROUNDDOWN(0xF8015000, CORE_MMU_PGDIR_SIZE) type IO_NSEC 0xf8000000 size 0x00200000
D/TC:0 add_phys_mem:578 Physical mem map overlaps 0xf8000000
D/TC:0 verify_special_mem_areas:516 SDP memory [3e800000 3ec00000]
D/TC:0 add_va_space:604 type RES_VASPACE size 0x00a00000
D/TC:0 add_va_space:604 type SHM_VASPACE size 0x02000000
D/TC:0 dump_mmap_table:711 type IO_NSEC va 0x3ac00000..0x3adfffff pa 0xf8000000..0xf81fffff size 0x00200000 (pgdir)
D/TC:0 dump_mmap_table:711 type IO_NSEC va 0x3ae00000..0x3affffff pa 0xf7000000..0xf71fffff size 0x00200000 (pgdir)
D/TC:0 dump_mmap_table:711 type TA_RAM va 0x3b000000..0x3bdfffff pa 0x3f200000..0x3fffffff size 0x00e00000 (pgdir)
D/TC:0 dump_mmap_table:711 type NSEC_SHM va 0x3c000000..0x3c1fffff pa 0x3ee00000..0x3effffff size 0x00200000 (pgdir)
D/TC:0 dump_mmap_table:711 type RES_VASPACE va 0x3c200000..0x3cbfffff pa 0x00000000..0x009fffff size 0x00a00000 (pgdir)
D/TC:0 dump_mmap_table:711 type SHM_VASPACE va 0x3ce00000..0x3edfffff pa 0x00000000..0x01ffffff size 0x02000000 (pgdir)
D/TC:0 dump_mmap_table:711 type TEE_RAM_RX va 0x3f000000..0x3f062fff pa 0x3f000000..0x3f062fff size 0x00063000 (smallpg)
D/TC:0 dump_mmap_table:711 type TEE_RAM_RW va 0x3f063000..0x3f1fffff pa 0x3f063000..0x3f1fffff size 0x0019d000 (smallpg)
D/TC:0 core_mmu_entry_to_finer_grained:753 xlat tables used 1 / 8
D/TC:0 core_mmu_entry_to_finer_grained:753 xlat tables used 2 / 8
I/TC:
D/TC:0 0 discover_nsec_memory:1163 Warning register_dynamic_shm() is deprecated, please use register_ddr() instead
D/TC:0 0 carve_out_phys_mem:292 No need to carve out 0x3e800000 size 0x400000
D/TC:0 0 carve_out_phys_mem:292 No need to carve out 0x3f000000 size 0x200000
D/TC:0 0 carve_out_phys_mem:292 No need to carve out 0x3f200000 size 0xe00000
D/TC:0 0 carve_out_phys_mem:292 No need to carve out 0x3ee00000 size 0x200000
I/TC: OP-TEE version: 3.13.0-77-gbc9618c0 (gcc version 9.2.1 20191025 (GNU Toolchain for the A-profile Architecture 9.2-2019.12 (arm-9.10))) #1 Mi 9. Jun 12:23:02 UTC 2021 aarch64
I/TC: Primary CPU initializing
D/TC:0 0 boot_init_primary_late:1245 Executing at offset 0 with virtual load address 0x3f000000
D/TC:0 0 call_initcalls:21 level 1 register_time_source()
D/TC:0 0 call_initcalls:21 level 1 teecore_init_pub_ram()
D/TC:0 0 call_initcalls:21 level 3 mobj_mapped_shm_init()
D/TC:0 0 mobj_mapped_shm_init:434 Shared memory address range: 3ce00000, 3ee00000
D/TC:0 0 call_initcalls:21 level 3 check_ta_store()
D/TC:0 0 check_ta_store:418 TA store: "early TA"
D/TC:0 0 check_ta_store:418 TA store: "Secure Storage TA"
D/TC:0 0 check_ta_store:418 TA store: "REE"
D/TC:0 0 call_initcalls:21 level 3 init_user_ta()
D/TC:0 0 call_initcalls:21 level 3 early_ta_init()
D/TC:0 0 early_ta_init:56 Early TA 023f8f1a-292a-432b-8fc4-de8471358067 size 24532 (compressed, uncompressed 42592)
D/TC:0 0 call_initcalls:21 level 3 verify_pseudo_tas_conformance()
D/TC:0 0 call_initcalls:21 level 3 tee_cryp_init()
D/TC:0 0 call_initcalls:21 level 4 tee_fs_init_key_manager()
D/TC:0 0 call_initcalls:21 level 5 peripherals_init()
D/TC:0 0 peripherals_init:123 enable LD021_1V8 source (pin 35) on LS connector
D/TC:0 0 spi_init:60 take SPI0 out of reset
D/TC:0 0 spi_init:67 PERI_SC_PERIPH_RSTDIS3: 0x0
D/TC:0 0 spi_init:77 PERI_SC_PERIPH_RSTSTAT3: 0xfffbfc3e
D/TC:0 0 spi_init:79 enable SPI clock
D/TC:0 0 spi_init:86 PERI_SC_PERIPH_CLKEN3: 0x0
D/TC:0 0 spi_init:89 PERI_SC_PERIPH_CLKSTAT3: 0x2403c1
D/TC:0 0 spi_init:101 configure gpio6 pins 0-3 as SPI
D/TC:0 0 spi_init:107 configure gpio6 pins 0-3 as nopull
D/TC:0 0 call_initcalls:21 level 6 mobj_init()
D/TC:0 0 call_initcalls:21 level 6 default_mobj_init()
I/TC: Primary CPU switching to normal world boot
I/TC: Secondary CPU 1 initializing
I/TC: Secondary CPU 1 switching to normal world boot
I/TC: Secondary CPU 2 initializing
I/TC: Secondary CPU 2 switching to normal world boot
I/TC: Secondary CPU 3 initializing
I/TC: Secondary CPU 3 switching to normal world boot
I/TC: Secondary CPU 4 initializing
I/TC: Secondary CPU 4 switching to normal world boot
I/TC: Secondary CPU 5 initializing
I/TC: Secondary CPU 5 switching to normal world boot
I/TC: Secondary CPU 6 initializing
I/TC: Secondary CPU 6 switching to normal world boot
I/TC: Secondary CPU 7 initializing
I/TC: Secondary CPU 7 switching to normal world boot
D/TC:2 tee_entry_exchange_capabilities:102 Dynamic shared memory is enabled
D/TC:2 0 core_mmu_entry_to_finer_grained:753 xlat tables used 3 / 8
D/TC:? 0 tee_ta_init_pseudo_ta_session:299 Lookup pseudo TA 7011a688-ddde-4053-a5a9-7b3c4ddf13b8
D/TC:? 0 tee_ta_init_pseudo_ta_session:312 Open device.pta
D/TC:? 0 tee_ta_init_pseudo_ta_session:329 device.pta : 7011a688-ddde-4053-a5a9-7b3c4ddf13b8
D/TC:? 0 tee_ta_close_session:512 csess 0x3f084a20 id 1
D/TC:? 0 tee_ta_close_session:531 Destroy session
D/TC:? 0 tee_ta_init_session_with_context:607 Re-open TA 7011a688-ddde-4053-a5a9-7b3c4ddf13b8
D/TC:? 0 tee_ta_close_session:512 csess 0x3f084870 id 1
D/TC:? 0 tee_ta_close_session:531 Destroy session

Any idea that what goes wrong?

from documentation.

What is the reason that there is no grub_uart2.cfg in patches_hikey/grub/

Your repo is not new enough. Do a git pull github master on patches_hikey and you'll see the file.

But hikey.mk (in comments) said that we can select UART2 for Normal/secure world console?

Are you just selecting whatever number you want or based on where you've connected your console cable to?

I changed hikey.mk and set NW_CONSOL_UART=3. Now it passes the "load fastboot1" but break again with:

Is CFG_SW_CONSOLE_UART still 0? Try changing CFG_NW_CONSOLE_UART to 0 too and see what happens.

from documentation.

Your repo is not new enough. Do a git pull github master on patches_hikey and you'll see the file.

I built just few days ago by REPO. After pulling as you said, the file appeared.

Are you just selecting whatever number you want or based on where you've connected your console cable to?

I have all three UARTS connected to three consoles to have NW and SW on different ones.

Is CFG_SW_CONSOLE_UART still 0? Try changing CFG_NW_CONSOLE_UART to 0 too and see what happens.

Setting both NW/SW_CONSOLE=0 solved the boot problem. And after getting grub_uart2.cfg the combination NW_CONSOLE=2 and SW_CONSOLE=0 works too.

Thanks for your help.

from documentation.