23-cpu Goto Github PK

academicpages.github.io

Github Pages template for academic personal websites, forked from mmistakes/minimal-mistakes

assembler_c

MIPS assembler for my C coding project

books

Reference Books_Computer

boom-attacks

Proof of concepts for speculative attacks using the BOOM core (https://github.com/riscv-boom/riscv-boom)

cache_template_attacks

This repository contains several tools to perform Cache Template Attacks

cpplinks

A categorized list of C++ resources.

demo_repo

digital_computer_design_prox

downfall

Recreate

flush-reload-attacks

For my research

flush_flush

This repository contains examples of Flush+Flush cache attacks

frameworks

Microarchitectural attack development frameworks for prototyping attacks in native code (C, C++, ASM) and in the browser

gem5

The official repository for the gem5 computer-system architecture simulator.

meltdown

This repository contains several applications, demonstrating the Meltdown bug.

minimal-risc-v-cpu

For reference

mips-32-revised

Design of two 32-bit Microprocessor architectures based on the MIPS Instruction Set

mips-assembler_in-c-

A MIPS Instruction Set Assembler in C

os-tutorial

How to create an OS from scratch

papers

Resourceful

parking-lot-lab-verilog

pdfs

Technically-oriented PDF Collection (Papers, Specs, Decks, Manuals, etc)

personal-portfolio

programming_tutorials_and_practice

ptlsim

Stable, non-KVM version of PTLsim.

reslient-architecture-lab

Allan Lab website

ridecore

RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.

riscv-cores-list

RISC-V Cores, SoC platforms and SoCs

rowhammer

Source code for testing the Row Hammer error mechanism in DRAM devices. Described in the ISCA 2014 paper by Kim et al. at http://users.ece.cmu.edu/~omutlu/pub/dram-row-hammer_isca14.pdf.

secsmt_artifact

The artifact for SecSMT paper -- Usenix Security 2022

simple-shell

A simple Linux shell (OS course work)